1. Field of the Invention
The present invention relates to an input/output buffer circuit. More particularly, it relates to an input/output buffer circuit wherein an input signal with voltage higher than its power source voltage is inputted to an input/output terminal
2. Description of Related Art
In recent years, fine structuralizing technology with respect to CMOS-structured semiconductor integrated circuits (referred as LSI hereinafter) has advanced and driving power source voltage level of LSI has been lowering progressively. However, lowering degree of driving power source voltage level differs due to product diversity. Therefore, a plurality of LSI power source different in voltage must be combined when structuring a system. It would be preferable if terminals of LSI power source different in voltage could be connected directly. In case connecting input/output terminals, there must be considered an aspect such that an input signal with voltage amplitude different from voltage amplitude of an output signal may be inputted. Accordingly, even if a signal with voltage amplitude same as or higher than voltage amplitude of power source voltage is inputted from an external, it must be secured that an unnecessary current path is never formed between the external and the power source voltage. Therefore, various circuit systems have been proposed until now.
An input/output buffer circuit 100 shown in FIG. 6 as a first prior art is a circuit carried by the 1992 October Edition of NIKKEI MICRODEVICES (pp.83-88).
An input/output mode switching signal CNT and an output data signal DOUT are inputted to a two-input NAND logic gate 11 and to a two-input NOR logic gate 12. An output terminal of the two-input NAND logic gate 11 is connected to a gate terminal G2 of a PMOS transistor P2 which is a driving transistor arranged at high voltage side through a transfer gate 3. An output terminal of the two-input NOR logic gate 12 is connected to a gate terminal of an NMOS transistor N2 which is a driving transistor arranged at low voltage side. A signal is outputted from an input/output terminal BUS by the PMOS transistor P2 and the NMOS transistor N2.
Furthermore, to a point between gate terminal G2 of the PMOS transistor P2 and the input/output terminal BUS, there is connected a PMOS transistor P3 a gate terminal of which is connected to power source voltage VDD. Thereby, this system works such that the gate terminal G2 of the PMOS transistor P2 is clamped together with input signal voltage VBUS so that the PMOS transistor P2 should be kept non-conductive in case an input signal with voltage higher than the power source voltage VDD is inputted from the input/output terminal BUS.
Furthermore, a PMOS transistor P1 and an NMOS transistor N1 constitute the transfer gate 3. The input/output terminal BUS is connected to a gate terminal of the PMOS transistor P1 and a gate terminal of the NMOS transistor N1 is connected to the power source voltage VDD. In case an input signal with voltage higher than power source voltage VDD is inputted from the input/output terminal BUS, this system sets the NMOS transistor N1 and the PMOS transistor P1 in an off state, whereby a path leading to an output terminal of the NAND logic gate 11 from the input/output terminal BUS by way of the PMOS transistor P3 is blocked.
With respect to a PMOS transistor P10, its gate terminal, drain terminal, and source terminal are connected to the input/output terminal BUS, power source voltage VDD, and N-well NW for the PMOS transistor P1 through P3, respectively. The connection of the source terminal and the N-well NW constitutes an N-well voltage control circuit VFM1 which adjusts voltage of the N-well NW depending on voltage inputted from the input/output terminal BUS. Furthermore, in case an input signal with high voltage is inputted from the input/output terminal BUS, NMOS transistors N3 and N4 are arranged to protect an NMOS transistor N2 and an input buffer circuit 4 from high voltage.
Here will be considered a case such that an input signal with voltage same as or higher than voltage obtained by adding threshold voltage Vthp of PMOS transistor to the power source voltage VDD is applied to the input/output terminal BUS of the input/output buffer circuit 100. Input signal voltage VBUS from the input/output terminal BUS is applied to the gate terminal of the PMOS transistor P10, whereby bias of the power source voltage VDD toward the N-well NW is blocked. Through a PN-junction constituted by drain terminals of the PMOS transistors P2 and P3 to which the input/output terminal BUS is connected, voltage of the N-well NW under this state approximates a value of the input signal voltage VBUS. As a result, a junction of the N-well NW and the source terminals of the PMOS transistors P2 and P10 to which the power source voltage VDD is connected turns into a reverse bias state and current-flow toward the power source voltage VDD through the PMOS transistors P2 and P10 is blocked.
Furthermore, since the power source voltage VDD is applied to the gate terminal of the PMOS transistor P3 the drain terminal of which is connected to the input/output terminal BUS, the PMOS transistor P3 becomes conductive and the gate terminal G2 of the PMOS transistor P2 is biased to the input signal voltage VBUS. Thereby, the PMOS transistor P2 is kept in an off state and a current path running through the PMOS transistor P2 is blocked.
Furthermore, since the gate terminal of the transfer gate 3 is connected to the input/output terminal BUS, the PMOS transistor P1 is kept in an off state. On the other hand, since its drain terminal is connected to the terminal G2 biased to the input signal voltage VBUS, the NMOS transistor N1 the gate terminal of which is connected to the power source voltage VDD operates with a saturation region. Accordingly, voltage same as or higher than the power source voltage VDD is never applied to a connection terminal to the NAND logic gate 11 through the transfer gate 3, whereby a current path leading to the power source voltage VDD through the PMOS transistors constituting the NAND logic gate 11 is not established.
As described, the input/output buffer circuit 100 directed to the first prior art prevents current from flowing from the input/output terminal BUS to the power source voltage VDD in case an input signal with voltage same as or higher than voltage obtained by adding the threshold voltage Vthp of PMOS transistor to the power source voltage VDD is applied to the input/output terminal BUS.
FIG. 7 shows an input/output buffer circuit 200 directed to a second prior art. In the input/output buffer circuit 200, there is not established a direct connection between an input/output terminal BUS and a gate terminal G1 of a PMOS transistor P1 which constitutes a transfer gate 3 corresponding to the first prior art. Instead, the input/output terminal BUS and the gate terminal G1 are connected to each other through a PMOS transistor P4 a gate terminal of which is connected to the power source voltage VDD. Furthermore, the gate terminal G1 is connected to ground voltage through an NMOS transistor N5. An input/output mode switching signal CNT inverted by an inverter logic gate 6 is inputted to a gate terminal of the NMOS transistor N5.
In the input/output buffer circuit 200, high-voltage proof elements are used for an NMOS transistor N2 and an input stage of and an input buffer circuit 4. Therefore, the NMOS transistors N3 and N4 arranged as protection from high voltage in the input/output buffer circuit 100 are not required in the second prior art. That is, the NMOS transistor N2 and the input buffer circuit 4 are directly connected to the input/output terminal BUS.
Furthermore, instead of the N-well voltage control circuit VFM1 in the input/output buffer circuit 100, an N-well voltage control circuit VFM 2 is arranged in the input/output buffer circuit 200. The N-well voltage control circuit VFM 2 is constituted by: a PMOS transistor P10 source terminal, drain terminal, and gate terminal of which are connected to the power source voltage VDD, the N-well NW, and the input/output terminal BUS, respectively, and; a PMOS transistor P11 source terminal, drain terminal and back-gate terminal, and gate terminal of which are connected to the input/output terminal BUS, the N-well NW, and the power source voltage VDD, respectively. Thereby, the system works such that voltage at the N-well NW can be switched between the power source voltage VDD and the input signal voltage VBUS depending on a value of input signal voltage VBUS at the input/output terminal BUS.
In the input/output buffer circuit 200, the PMOS transistor P4 the gate terminal of which is connected to the power source voltage VDD becomes conductive in case an input signal with voltage same as or higher than voltage obtained by adding the threshold voltage Vthp of PMOS transistor to the power source voltage VDD is applied to the input/output terminal BUS. Further on, in this case, an input/output mode switching signal CNT is high logic level and an NMOS transistor N5 is in an off state. Therefore, an input signal from the input/output terminal BUS is applied to the gate terminal G1 of the PMOS transistor P1 and the PMOS transistor P1 is turned off for sure. Accordingly, a current path leading to the power source voltage VDD through the PMOS transistor constituting the NAND logic gate 11 is not established. Furthermore, it is same as the first prior art that a current path leading to the power source voltage VDD through a PN junction of the PMOS transistors P2 and P10 and a current path leading to the power voltage VDD through the PMOS transistor P2 are blocked. The input/output buffer terminal 200 thus prevents current from flowing into the power source voltage VDD from the input/output terminal BUS in case an input signal with voltage same as or higher than voltage obtained by adding the threshold voltage Vthp of PMOS transistor to the power source voltage VDD is applied to the input/output terminal BUS.
However, on condition that, as for absolute value, a threshold Vthp of PMOS transistor is lower than a threshold Vthn of NMOS transistor, i.e., (Vthn greater than Vthp), due to device structure of LSI, manufacturing conditions, or the like, the input/output buffer circuits 100 and 200 may face a problem such that unnecessary inflow current IBUS flows into the input/output terminal BUS in case a value of an input signal voltage VBUS inputted to the input/output terminal BUS is not optimum.
There will be described conditions that inflow current IBUS flows specifically by referring to gate terminal voltage VG2 at the PMOS transistor P2 responsive to the input signal voltage VBUS (see FIG. 8), and inflow current IBUS responsive to the input signal voltage VBUS (see FIG. 9).
Here will be considered a case that the input/output buffer circuit 100 (see FIG. 6) works as input buffer and receives an input signal from the input/output terminal BUS. In this case, the PMOS transistor P2 constituting an output buffer section must be kept in an off state. In case the input signal voltage VBUS is same as or higher than (VDD+Vthp), the PMOS transistor P1 is turned off and the PMOS transistor P3 becomes conductive, whereby the gate terminal voltage VG2 is equivalent to the input signal voltage VBUS ({circle around (1)} in FIG. 8). Furthermore, in case the input signal voltage VBUS is same as or lower than (VDDxe2x88x92Vthp), though the PMOS transistor P3 is turned off, the PMOS transistor P1 becomes conductive. Therefore, the gate terminal voltage G2 is equivalent to the power source voltage VDD ({circle around (3)} in FIG. 8). Accordingly, in both cases, namely, (VBUS greater than VDD+Vthp) ({circle around (1)} in FIG. 8, and (VBUS less than VDDxe2x88x92Vthp) {circle around (3)} in FIG. 8, the PMOS transistor P2 is kept in an off state. Accordingly, inflow current IBUS does not flow from the input/output terminal BUS ({circle around (1)} and {circle around (3)} in FIG. 9).
However, in case voltage level of the input signal voltage VBUS is between (VDDxe2x88x92Vthp) and (VDD+Vthp), the PMOS transistors P1 and P3 are in an off state. Consequently, the NMOS transistor N1 which becomes conductive depending on saturation characteristic applies voltage minimum of which is (VDDxe2x88x92Vthp) to the gate terminal G2 ({circle around (2)} in FIG. 8). On condition that it is (Vthn greater than Vthp), the PMOS transistor P2 cannot be kept in an off state and this situation allows inflow current IBUS to flow from the input/output terminal BUS. This is a problematic aspect of the prior art.
That is, in case voltage level of the input signal voltage VBUS is between (VDDxe2x88x92Vthp) and (VDD), unnecessary current IBUS flows out from the power source voltage VDD in the LSI through the input/output terminal BUS ({circle around (2)}A in FIG. 9) whereas in case between (VDD) and (VDD+Vthp), unnecessary current IBUS flows into the internal of the LSI from the input/output terminal BUS ({circle around (2)}B in FIG. 9). This is also a problematic aspect of the prior arts.
As for the input/output buffer circuit 200, in case of (VBUS greater than VDD+Vthp), the PMOS transistor P1 is turned off and the PMOS transistor P3 becomes conductive, whereby the PMOS transistor P2 is kept in an off state and inflow current IBUS does not flow from the input/output terminal BUS. This aspect is similar to the input/output buffer circuit 100.
However, in case of (VBUS less than VDD+Vthp), the PMOS transistor P3 as well as the PMOS transistor P4 are turned off, whereby the gate terminal G1 of the PMOS transistor P1 turns into a floating state. In case the gate terminal voltage VG1 is kept between (VDDxe2x88x92Vthp) and (VDD+Vthp) under this situation, the PMOS transistor P2 cannot be kept in an off state, similar to the input/output buffer circuit, inflow current IBUS flows from the input/output terminal BUS. This is also a problematic aspect. Furthermore, with respect to the input/output buffer circuit 100, since presence/absence of the inflow current IBUS depends on the gate terminal voltage G1 in a floating state, there occurs a problem that inflow current IBUS may flow even though it is (VBUS less than VDDxe2x88x92Vthp) where the inflow current IBUS is not supposed to flow.
Furthermore, in case the structure of an interface circuit to be connected to the input/output terminal BUS is not an appropriate one, inflow current IBUS flows due to a connection to the interface circuit. As a result, the input/output terminal BUS cannot be set to a predetermined voltage level.
FIG. 10 shows a case that an interface circuit including a pull-down resistance Rpd is connected to the input/output terminal BUS. A switch element SW1 is arranged there so as to apply external voltage to the input/output terminal BUS. When the switch element SW1 becomes conductive and the external voltage Vt is applied to the input/output terminal BUS, if voltage level of the external voltage Vt is (VDDxe2x88x92Vthpxe2x89xa6Vt less than VDD+Vthp), the PMOS transistor P2 becomes conductive. In case the switch element SW1 is turned off and the pull-down resistance Rpd is connected to the input/output terminal BUS from this situation, if a divided voltage ratio of an ON-resistance RP2 of the PMOS transistor P2 and the pull-down resistance Rpd is not an appropriate one, voltage of (VDDxe2x88x92Vthpxe2x89xa6VBUS less than VDD+Vthp) may be continuously applied. In this case, unnecessary current IBUS keeps flowing to the external and the input signal voltage VBUS at the input/output terminal BUS does not reach low level voltage which is pulled-down. This is a problematic aspect. The input signal voltage VBUS at this moment satisfies an expression as below.
VBUS=VDDxc3x97Rpd/(Rpd+RP2)
This is problematic because voltage level of (VDDxe2x88x92Vthpxe2x89xa6VBUS less than VDD+Vthp) is kept.
FIG. 11 shows a case that an interface circuit including a pull-up resistance Rpu is connected to the input/output terminal BUS. A switch element SW2 is arranged there so as to apply ground voltage to the input/output terminal BUS. In case terminal voltage VBUS is (VDDxe2x88x92Vthpxe2x89xa6Vt less than VDD+Vthp) when the switch element SW2 is turned off and the input/output terminal BUS is pulled up to the external voltage Vt, the PMOS transistor P2 becomes conductive. If a divided voltage ratio of an ON-resistance RP2 of the PMOS transistor P2 and the pull-up resistance Rpu is not an appropriate one, voltage of (VDDxe2x88x92Vthpxe2x89xa6VBUS less than VDD+Vthp) may be continuously applied. In this case, unnecessary current IBUS keeps flowing in from the external and the input signal voltage VBUS at the input/output terminal BUS does not reach high level voltage which is pulled-up. The input signal voltage VBUS at this moment satisfies an expression as below.
VBUS=(Vtxe2x88x92VDD)xc3x97RP2/(Rpu+RP2)+VDD
This is problematic because voltage level of (VDDxe2x89xa6VBUS less than VDD+Vthp) is kept.
The present invention, attempted to resolve the above-noted problems of the prior arts, is intended to provide an input/output buffer circuit capable of preventing unnecessary current from flowing between power source voltage and an input signal applied externally, wherein an input signal with voltage higher than the power source voltage is inputted to an input/output terminal.
In order to achieve the above-stated object, in accordance with one aspect of the present invention, there is provided an input/output buffer circuit to which an input signal with voltage same as or higher than its power source voltage is possibly inputted through an input/output terminal when it is an input mode, wherein voltage at a gate terminal of a driving PMOS transistor, which drives the input/output terminal when it is an output mode, is set to an input signal voltage when the input signal voltage is in a first region corresponding to voltage values same as or higher than voltage obtained by adding predetermined voltage to the power source voltage, and voltage at the gate terminal of the driving PMOS transistor, which drives the input/output terminal when it is an output mode, is set to the power source voltage when the input signal voltage is in a second region corresponding to voltage values lower than the voltage obtained by adding predetermined voltage to the power source voltage.
In the input/output buffer circuit directed to the one aspect of the present invention, setting voltage at the gate terminal of the driving PMOS transistor for an input/output terminal is switched depending on input signal voltage to be inputted to the input/output terminal under an input mode. In the first region, namely, when input signal voltage is same as or higher than the voltage obtained by adding predetermined voltage to the power source voltage, gate terminal voltage of the driving PMOS transistor is equal to input/output terminal voltage. In the second region, namely, when input signal voltage is lower than the voltage obtained by adding predetermined voltage to the power source voltage, gate terminal voltage of the driving PMOS transistor is equal to the power source voltage.
Thereby, even if a value of the input signal voltage to be inputted to the input/output terminal varies under an input mode, voltage set at the gate terminal of the driving PMOS transistor keeps the driving PMOS transistor non-conductive state. Therefore, an unnecessary current path is not formed between the input/output terminal and the power source voltage through the driving PMOS transistor. Thereby, unnecessary inflow/outflow of current from the input/output terminal can be avoided. Furthermore, since there is no unnecessary inflow/outflow of current, the input/output terminal can be set to predetermined voltage level.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in conjunction with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.